Features
?
?
?
?
?
?
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 1.8 (V CC = 1.8V to 5.5V)
20MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
?
?
?
?
?
?
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
SPI Serial
Electrically
Erasable and
Programmable
Read-only Memory
128K (16,384 x 8)
Description
The Atmel ? AT25128B/256B provides 131,072/262,144-bits of serial electrically eras-
able programmable read only memory (EEPROM) organized as 16,384/32,768 words
of 8-bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead
UDFN packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V).
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
256K (32,768 x 8)
Atmel AT25128B
Atmel AT25256B
Table 0-1.
Pin Configurations
Pin
Function
CS
8-lead SOIC
1 8
V CC
8-lead TSSOP
CS 1 8
V CC
CS
SCK
Chip Select
Serial Data Clock
SO
WP
GND
2
3
4
7
6
5
HOLD
SCK
SI
SO
WP
GND
2
3
4
7
6
5
HOLD
SCK
SI
SI
Serial Data Input
SO
Serial Data Output
8-lead UDFN
8-ball VFBGA
GND
V CC
WP
Ground
Power Supply
Write Protect
V CC
HOLD
SCK
SI
8
7
6
5
1 CS
2 SO
3 WP
4 GND
V CC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
HOLD
Suspends Serial Input
Bottom View
Bottom View
Block Write protection is enabled by programming the status register with top ?, top ?
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is
provided via the WP pin to protect against inadvertent write attempts to the status reg-
ister. The HOLD pin may be used to suspend any serial communication without
resetting the serial sequence.
8698C–SEEPR–8/11
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相关代理商/技术参数
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